Single-Cycle MIPS Processor in Logisim-evolution

The single-cycle MIPS datapath is the most-taught processor design in computer architecture courses: every instruction completes in exactly one clock cycle. This guide maps each block of the classic textbook diagram to a real Logisim-evolution component, so you can build the thing the lectures only draw on slides.

This is an advanced project. Work through Building a Simple CPU first — the ideas are the same, but MIPS removes the multi-state control unit and does everything combinationally in one cycle.

The five blocks and their components

  • Program Counter — a Register (Memory library), 32 bits, holding the instruction address. A small Adder adds 4 every cycle (MIPS instructions are 4 bytes).
  • Instruction Memory — a ROM: 32-bit data width, addressed by the PC. This is where your test program lives.
  • Register File — the Register File component (Memory library): 32 registers of 32 bits, with two read ports and one write port. Feed it the rs/rt fields for reads and the rd field for writes.
  • ALU — the ALU component (Arithmetic library): takes two 32-bit operands and an operation select, produces the result plus a zero flag.
  • Data Memory — a RAM (Memory library) for lw/sw.

Splitting the instruction

Use splitters to carve the 32-bit instruction into fields: opcode (bits 31–26), rs (25–21), rt (20–16), rd (15–11), and the 16-bit immediate. A Decoder on the opcode generates the control lines: which ALU operation, whether the second ALU operand is a register or the sign-extended immediate, whether to write the register file, whether to access data memory.

Walk through one instruction of each type

R-type (e.g. add $t0, $t1, $t2): PC → ROM gives the instruction; register file reads $t1 and $t2; ALU adds; result writes back to $t0. The immediate path and data memory sit idle.

Load (lw $t0, 8($t1)): ALU adds $t1 + 8 to form the address; data memory reads; the memory output — not the ALU output — is multiplexed back into the register file.

Branch (beq $t1, $t2, label): ALU subtracts $t1 − $t2; if the zero flag is set, a multiplexer at the PC input selects PC + branch offset instead of PC + 4. This is the Comparator idea from the earlier tutorial, inside the ALU.

Testing with a tiny program

Hand-assemble 4–6 instructions (add, sub, lw, sw, beq), type the machine code into the ROM’s hex editor, and single-step with Simulate → Tick Once while watching the register file. Better: open Simulate → Chronogram first (remember it needs a clock labeled sysclk in the circuit as its time base) and record the PC, the instruction word, and the ALU result — one glance shows whether each instruction did its job. See the Chronogram tutorial for the setup.

Honest scope

  • Implement a subset of MIPS (the five instruction types above). Full MIPS includes exceptions, multiplication, and privileged instructions — nobody’s class project does those.
  • Single-cycle means the clock must be slow enough for the longest path (load word). That is the entire point of the later pipelining lectures.
  • Sign-extend the 16-bit immediate to 32 bits before it reaches the ALU — forgetting this breaks every lw with a large offset.

When it works, you have done the thing the course is actually about. The victory lap is putting it on a real FPGA.