Chronogram & Timing Analysis in Logisim-evolution

Watching LEDs blink tells you that a circuit works. The Chronogram — Logisim-evolution’s built-in timing diagram — tells you when everything happens: signal waveforms plotted against time, so you can see propagation delays, glitches, and the exact ordering of events across clock edges. It is the tool you reach for the moment “it should work” meets “it doesn’t”.

The one requirement: a clock named sysclk

The chronogram module uses a dedicated time base. Per the official documentation, your circuit must contain a clock whose Label is sysclk — it does not have to be connected to anything; it just has to exist. This is the step everyone misses:

  1. Place a Clock (Wiring library) anywhere on the canvas.
  2. In its attributes, set Label to sysclk (exact spelling, lowercase).
  3. If your circuit already has a main clock driving the logic, keep it — the sysclk clock is only the chronogram’s time reference.

Step 1 — Choose the signals to record

  1. Open Simulate → Chronogram. A signal-selection window appears.
  2. Add the signals you care about: click wires or component outputs in your circuit to add them to the list. Good first picks are the clock, the counter output, and any carry or control line you are debugging.
  3. Confirm the selection. The chronogram window opens with your signals listed on the left and an empty timeline on the right.

Step 2 — Run and read the waveforms

The chronogram toolbar mirrors the simulation controls: start/stop the simulation, advance a tick, and step the sysclk clock. As the simulation runs, waveforms draw from left to right. What to look for:

  • Glitches: narrow spikes where a signal briefly flips and returns — usually a race between two paths arriving at different times. In simulation they are often harmless; on real silicon they can clock a flip-flop by accident.
  • Skew in ripple chains: record every bit of a ripple counter (like the one in the digital clock tutorial) and watch the bits change one after another instead of together. That stagger is propagation delay made visible.
  • Setup/hold around clock edges: zoom in where your data changes relative to the clock edge. If data is still moving when the clock rises, your design is living dangerously.

When simulation is not enough: measure the real thing

The chronogram shows what the model does. Real silicon adds analog reality — noise, ringing, metastability — that no simulator draws for you. When a circuit works in Logisim-evolution but misbehaves on the bench, you need to capture the actual signals:

A logic analyzer records the real digital waveforms on your board’s pins — the physical counterpart of the chronogram window. If you are doing the FPGA workflow or debugging timing on real hardware, this is the instrument that answers “what is the pin actually doing”.

Compare logic analyzers

A multimeter is the companion for everything static: verifying supply rails, checking continuity, confirming a pin is really at the voltage you think.

Compare multimeters

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Troubleshooting the chronogram itself

  • Window opens but stays empty: no clock labeled sysclk in the circuit. Add one per the section above.
  • Signals missing from the list: you have to add them in the selection window before the timeline starts recording; it does not retroactively capture.
  • Simulation slows to a crawl: recording many wide buses every tick is expensive. Record fewer signals, or record a single representative bit per bus.

Go further: use the chronogram to debug the carry chain in the digital clock, or to verify each instruction of your MIPS processor cycle by cycle.