How to Build a Simple CPU in Logisim-evolution

A CPU looks intimidating until you see that it is only two halves: a datapath that moves and transforms numbers, and a control unit that tells the datapath what to do, step by step. This guide walks through an 8-bit accumulator machine — the smallest design that still honestly deserves the name “CPU”. It will not run on the first try. That is normal; debugging it is where the learning happens.

Before starting, you should be comfortable with the ROM, the Comparator, and tunnels and splitters — this project uses all three heavily.

The datapath: registers, ALU, buses

The datapath holds the numbers and does the math. For an 8-bit accumulator CPU you need:

  • Program Counter (PC) — a Counter (Memory library) holding the address of the current instruction.
  • Instruction ROM — a ROM whose address input is the PC. Its output is the instruction being executed.
  • Instruction Register — a Register (Memory library) that latches the ROM output so it stays stable while the instruction runs.
  • Accumulator — another Register holding the working value every operation uses.
  • ALU — build it from Adder and Subtractor (Arithmetic library) plus a Comparator for the zero/equal flag. A couple of Multiplexers select which result goes back to the accumulator.
  • Data RAM — a RAM (Memory library) for variables the program reads and writes.

Connect these with 8-bit buses. Use tunnels for the buses — a CPU wired with physical wires becomes uneditable within an hour.

The control unit: a state machine that sequences everything

Each instruction takes several clock ticks: fetch the instruction, decode it, execute it. The control unit is a small state machine — a Counter cycling through states 0–3, feeding a Decoder (Plexers library) whose outputs are the individual control lines:

  1. State 0 – Fetch: PC drives the ROM address; latch the ROM output into the Instruction Register; increment the PC.
  2. State 1 – Decode: split the instruction register into opcode and operand (a splitter does this); the opcode selects the ALU operation via multiplexers.
  3. State 2 – Execute: enable the accumulator’s clock so it latches the ALU result; for load/store, enable the RAM’s write line instead.
  4. State 3 – Cleanup: clear one-shot signals, return to state 0.

Keep the instruction set tiny at first: LOAD addr, STORE addr, ADD addr, JUMP addr, HALT. Five instructions are enough to run a real program — say, one that adds two numbers stored in RAM.

Testing: write a program into the ROM

Assemble your test program by hand (each instruction is just a few bytes: opcode + address), type it into the ROM’s hex editor, reset the simulation (Simulate → Reset Simulation, Ctrl+R), enable ticks, and watch the accumulator. When the result is wrong — and it will be, the first times — open Simulate → Chronogram and record the control lines to see which state misbehaves. The Chronogram tutorial covers exactly this debugging workflow.

Common first-CPU bugs

  • PC increments twice per instruction: the increment signal is level-sensitive and fires on more than one state. Gate it so it is only active in the fetch state.
  • Instruction register latches garbage: ROM output needs a tick to settle after the PC changes. Latch it on the next state, not the same one that changed the PC.
  • ALU output fights the bus: two drivers on one tunnel or wire show up orange. Exactly one component may drive a bus at a time — multiplexers, not wishes, decide.

Go further

The classic next step is the Single-Cycle MIPS Processor, which replaces the multi-state control unit with a combinational one and runs real MIPS instructions. And when your CPU finally adds 2 + 2 correctly, run it on a real FPGA — the circuit you drew becomes an actual chip. If you want the theory behind this datapath in textbook form, Digital Design and Computer Architecture by Harris & Harris walks through the same accumulator-to-MIPS progression chapter by chapter.

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