Sequence Detector (101/1101) in Logisim-evolution

Detecting a bit sequence like 101 or 1101 in a serial stream is the standard finite-state-machine lab. The design method is always the same:

Step 1: Draw the state diagram

For a 101 detector you need three states: S0 (no progress), S1 (just saw “1”), S2 (just saw “10”). From each state, draw transitions for input 0 and input 1, marking which transition asserts the output. Overlapping sequences (e.g. 10101 contains two detections) are handled by choosing the right fallback transitions — this is where most students lose marks, so draw carefully.

Step 2: Encode states and build the excitation table

With two D flip-flops you get four state codes (00, 01, 10). Write the table: current state + input → next state + output.

Step 3: Implement with D flip-flops

Derive the D input equations (K-maps or Project → Analyze Circuit), build the combinational part from gates, and close the loop through two D flip-flops (Memory library) sharing one clock. Enable ticking with Simulate → Ticks Enabled (Ctrl-K).

Moore vs Mealy

In a Moore machine the output depends on the state only (output changes on the clock edge); in a Mealy machine it depends on state and input (output can change mid-cycle). Instructors love asking for both — the circuits differ only in the output logic.

If the flip-flops power up in the wrong state, see troubleshooting (DFF initialization).

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Related: traffic light controller (bigger FSM) · flip-flops