Instruction Decoder in Logisim-evolution

The instruction decoder is the part of a CPU’s control unit that translates an opcode (the “what to do” bits of an instruction) into control signals that steer the datapath. If you are building the CPU from our simple CPU tutorial, this page shows how to decode a 6-bit opcode into signals like these:

• RWE (register write enable) — write the result back into the register file
• ALUop (2 bits) — tell the ALU which operation to perform
• DWE (data-memory write enable) — allow a store to data memory
• MuxA (ALU source select) — choose between a register value and an immediate constant as the ALU input

Two ways to build it

Option A: Decoder component + OR gates (small opcodes)

For a handful of opcodes, place a Decoder from the Plexers library with 3 select bits. Each output line means “this opcode is active”. OR the relevant lines together to form each control signal. This is easy to read, which is why textbooks use it.

Option B: ROM lookup table (recommended for 6-bit opcodes)

A 6-bit opcode has 64 possible values — wiring 64 decoder outputs by hand is painful. Instead, use a ROM as a lookup table:

1. Place a ROM. Set its address width to 6 and its data width to the number of control signals (for example 5: RWE, ALUop[1:0], DWE, MuxA).
2. Connect the 6 opcode bits to the ROM’s address input.
3. Double-click the ROM to open the hex editor and fill one row per opcode: each row holds that instruction’s control-signal pattern. Our ROM tutorial walks through the hex editor.
4. Split the ROM’s data output with a Splitter so each control signal gets its own named wire (use tunnels to keep it readable).

The ROM approach mirrors how real control units are documented: one table, one row per instruction. When you add a new instruction, you edit the table — not the wiring.

Testing the decoder

Feed each opcode from a Constant or input pins, then check the control outputs with Probes. A quick sanity check: the R-type opcode should assert RWE and set ALUop to “add”, while a store opcode should assert DWE and MuxA instead. See combinational analysis if you want to verify the logic formally.